The present inventions relate to integrated circuit devices and processes, and particularly to CMOS devices and processes which are highly resistant to latchup.
Background: Latchup
Latchup is one of the basic problems of CMOS technology. Consider the sequence of a PMOS source region, the surrounding N-well region, a p-well region (or p-type epitaxial layer), and an NMOS source region. This sequence of regions will inevitably occur in normal bulk CMOS designs, and it defines a thyristor. This thyristor is referred to as "parasitic," since it is not created intentionally. A thyristor is a bipolar device which has an extremely low on-resistance. Once the thyristor turns on (or "fires"), it will remain on for as long as it can draw its minimum holding current. This behavior is extremely undesirable in integrated circuits, since when such a parasitic thyristor fires it may destroy the integrated circuit (by drawing excessive current), or may rapidly discharge a portable system's battery, or may simply cause the chip to remain in a "stuck" condition, and hence become unusable, until the power supply is disconnected.
Any thyristor can be regarded as a merger of a PNP transistor with an NPN transistor, and this model is frequently a convenient way to analyze the properties of the parasitic thyristor. The gain of the parasitic thyristor is equal to the product of the gains of the bipolar transistors, so degrading the gain of either parasitic bipolar helps to degrade the parasitic thyristor. (Although the thyristor reaches low impedance once triggered, it is still useful to analyze the small-signal "gain" of the thyristor in considering triggering: lower gain will mean that a larger input energy is required to trigger the thyristor. Since voltage transients are always present, it is desirable to provide some margin of immunity against triggering by transients.) There are several ways to approach the device-level properties of the thyristor: either the holding current can be increased, or the firing voltage can be increased, or the gain of one or both of the parasitic bipolar transistors can be degraded, or low-resistance shunting elements can be added to bypass one or both of the parasitic bipolar transistors (so that the current driven by one transistor does not all appear as base current on the other).
Background: Punchthrough
Another of the basic problems in normal CMOS (or almost any other field-effect transistor formed in bulk material) is punchthrough: when the depletion regions around the source/drain boundaries spread sufficiently to touch, then current can bypass the channel region, i.e. the source and drain are essentially shorted together.
Innovative CMOS Device and Process
The present application provides a CMOS device and process in which the source/drain regions are polysilicon, and are dielectrically isolated from the well regions. This structure can be obtained, for example, by depositing the first layer of polysilicon under very high temperature conditions (essentially the same as those normally used for epitaxial deposition), so that the first polysilicon layer is formed epitaxially (as monocrystalline silicon) over exposed regions, and as polycrystalline material over oxide. An oxide is grown on the surface of the deposited layer, and a second polysilicon layer is then deposited, under normal conditions, to form the gate layer. After the second polysilicon layer has been patterned, source/drain implants are then made into the first (intrinsic) polysilicon layer to form source/drain implants. Thus, the first polysilicon layer will contain both N+ and P+ regions, and if desired, may also include intrinsic regions. The intrinsic regions permit high-resistivity resistors to be built in the first polysilicon layer at no extra processing cost (assuming that N+ and P+ masks are used for separate NMOS and PMOS source/drain patterning, as is now usual.)
Thus, in this structure, there is no possibility whatsoever of junction spiking. Moreover, the possibility of latch-up is greatly reduced, since the source/drain regions form a junction to the well only in locations which are immediately adjacent to the channel. Optionally, the source/drain implantation can be done as a two-step process, using sidewall dielectrics for self-aligned masking of the N+ implant, just as is conventionally done to form LDD regions.
Depending on where the junction boundaries are located, the use of polysilicon source/drain regions according to the present invention may not absolutely remove the parasitic thyristor, but it does permit the junction locations to be carefully controlled. Using control of this positioning, the basewidth of both of the two parasitic bipolars can be made huge, so that the gain of each of the parasitic bipolars is extremely low. This basewidth can be adjusted so that the parasitic thyristor will not fire under any normal conditions (except under applied voltages which would cause immediate breakdown of other parts of the integrated circuit anyway).
As usual, VT implants are used to adjust the threshold voltages of the NMOS and PMOS devices. Thus, in this device architecture, the electrical function of the well regions becomes minor. (Their primary purpose is to provide seed material for the epitaxial growth of the channel region.) The sole electrical function of the well regions is to provide back biasing for the transistors.
Because the depth and doping of the wells is electrically much less important than in a conventional CMOS process, these parameters can be optimized for other components in a mixed process. For example, in a bipolar/CMOS/DMOS or a BiCMOS process, well depth and doping can be chosen with complete freedom to optimize the gain and breakdown characteristics of the bipolar devices. An important advantage of this device structure is that it affords a highly planar structure, since the poly2 gate stripe is nested in between the elevated source/drain regions in the first polysilicon layer.
Note that the chance of punch-through is also reduced, since the source/drain junctions do not extend downwardly into the well (if at all) as deeply as the prior art junctions do.
Thus features and advantages of various embodiments of the disclosed inventions include:
1. This structure reduces the capacitance between the body and both the source and the drain. PA1 2. The spacings between the diffused source/drain regions can be reduced, since these diffused regions are in polysilicon, and can be laterally separated by etching. PA1 3. Contact spiking through source/drain regions is no longer a concern, since all source/drain regions now have a layer of dielectric beneath them. PA1 4. Susceptibility to latch-up is reduced, since there is less (if any) of the source/drain diffusions in contact with the body regions. PA1 5. Susceptibility to hot carrier effects becomes less of a problem, since the drain region near the gate is polysilicon. Electrons have a lower velocity in polysilicon, which makes it more difficult for them to tunnel into the gate dielectric. PA1 6. The process steps used to provide the structures can be included in a more complex process sequence such as BiCMOS technology. PA1 7. The basic structure can be used in a variety of technologies, including NMOS, PMOS, CMOS, DMOS, or JFET.
Note that the edge of the oxide which defines the active region is not self-aligned to the gate in the second polysilicon layer. This introduces an additional design parameter. For instance, by making the second polysilicon gate wider than the oxide opening which defines the width of the crystalline silicon region, a degree of underlap is achieved which may cause a region of more lightly doped silicon, having a doping determined by lateral diffusion which becomes lighter going from the drain to the channel, and thus automatically provides a lightly doped drain profile to reduce hot carrier effects. Manipulation of this kind can be used in combination with the conventional side-wall-oxide-defined LDD regions, or even with a conventional double-diffused graded drain (formed by differential diffusion of phosphorous plus arsenic). Unlike the conventional LDD and graded drain techniques, this new technique permits ASYMMETRY in the transistor, in that the source and drain regions do not have to have exactly the same profile. Thus the potential contour of the drain boundary can be optimized without adding series resistance on the source side.
The thickness of the oxide which is used to determine the size of the monocrystalline silicon region is not critical. Thus, again, the thickness of this oxide can be determined by other considerations. For example, in smart power processes, the oxide layer can be used for the gate oxide of VDMOS or LDMOS high voltage and/or high-current transistors.
In one class of embodiments, this device structure can be used for just one of the device types in a CMOS integrated circuit. For example, by making the PMOS devices, but not the NMOS devices, in the poly1/epi layer, the NMOS and PMOS devices can actually be overlapped with each other. (The removal of the PMOS devices from the substrate is enough to inhibit latchup.) Thus, this provides significant advantages in density.
Further advantages in density are provided by the improved tolerance to contact misalignment. In conventional structures, a misaligned contact to the active area may chew through the corner of the field oxide to expose the channel stop diffusion (and thus potentially cause a short circuit). Similarly, a misaligned contact to polysilicon over active may make contact to the source/drain region. Normally design rules are selected to make these mishaps adequately unlikely, but the present invention permits these design rules to be relaxed (and hence improves density and/or yield).
In the presently preferred embodiment, the oxide which is used to define apertures where crystalline material will be grown is not itself field oxide, but is used in combination with a LOCOS field oxide which covers the margins of the P-well and N-well regions. Alternatively, various other techniques for field isolation can be used, or it may even be possible to eliminate the field oxide (IF the combination of on-chip voltages, dielectric thickness under the polysilicon lines, and substrate doping under the polysilicon lines combine, according to well-known formulas, so that the parasitic transistors do not turn on).
In a further class of embodiments, the same process flow can be used to provide a self-aligned channel stop implant. To implement this, a channel stop implant is performed (with an energy which is selected to reach through the oxide thickness), after the gate structure in poly-2 is in place. (Depending on the desired lateral spacing of the channel stop diffusions, this implant can be performed with or without sidewall spacers on the gate.) This provides an important further step toward a process with no thick field-oxide at all. Such a process provides important advantages of reduced topography, reduced diffusion length of buried layers, and reduced process complexity.